Theme 4: Physics, Mechanisms, and Device Prototyping

Lead: Roger Lake, UC Riverside

This theme aims to address the problems of reducing energy dissipation, continued scaling, and improved performance of analog/memory/logic/sensor and integrated circuits by exploiting the unique properties of the oxide, metal, and vdW material systems, low-dimensionality, collective states, and quantum states. The interplay of material properties from Themes 1–3 particularly atomic layer accurate interfaces, new multi interfacial phase transitions controllable by the interplay of strain, electric and magnetic fields, will be used in this theme for exploration of device physics, device mechanisms and device prototyping. As such, the theme will be cognizant of ITRS beyond CMOS challenges such as reducing energy dissipation, continued scaling, and improved performance of analog/memory/logic/sensor and integrated circuits. Furthermore, this theme will drive theme pathways and benchmarks.

The Principal Investigators contributing to this theme include:

  • Roger Lake (UCR)
  • H.S. Philip Wong (Stanford)
  • Ki Wook Kim (NCSU)
  • Sayeef Salahuddin (UCB)
  • Alexander Khitun (UCR)
  • Alejandro Strachan & Gerhard Klimeck (Purdue)
  • Joerg Appenzeller (Purdue)
  • James Bain & Marek Skowronski (CMU)
  • Will Hughes (Boise State)